Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a semiconductor memory in which memory cells are refreshed again through an amplifier. The invention additionally relates to a method for operating such a semiconductor memory.
In dynamic semiconductor memories, each of the memory cells includes a selection transistor with a storage capacitor. The storage capacitor can be connected to a bit line through the selection transistor, so that the charge content of the memory cell can be read out or written in. The selection transistor can be driven through a word line. By activation of the word line and selection of the bit line, an access is made to the memory cell disposed at the crossover of the word and bit lines. A sense amplifier is connected to the bit line so that the relatively small charge content of the memory cell is amplified by the sense amplifier to form a full-level signal and is, thus, available for further processing in the semiconductor memory.
The charge content of the storage capacitor is volatile due to the incomplete insulation of the capacitor within the integrated circuit and the leakage currents established as a result. Therefore, the charge content must be refreshed again with specific time intervals. In dynamic semiconductor memories, the operation of refreshing them again is also referred to as refresh. During the refresh, the bit line is firstly brought to an equalization level lying, for example, in the middle of the fully driven high level and low level. Afterward, as a result of the selection transistor being switched on, the capacitor of the memory cell to be refreshed is connected to the bit line. The charge content of the storage capacitor slightly displaces the equalization level of the line in accordance with the stored charge state. Such asymmetry is then amplified by the sense amplifier and subsequently output as an amplified signal onto the bit line and thereby written back again to the storage capacitor of the memory cell to be refreshed. Such an operation is likewise applied to all the other memory cells. If the quantity of charge stored in the memory cell under consideration has decreased again, the refresh operation is repeated on the memory cell.
It should be stressed that the parasitic capacitance formed by the bit line is a multiple of the relatively small capacitance of the storage capacitor of a connected memory cell. By way of example, the ratio of bit line capacitance to the capacitance of one of the memory cells amounts to 10:1. During a refresh operation, the bit line capacitance, proceeding from the equalization level, is subjected to charge reversal to a high or low level in accordance with the stored data value and is subsequently returned to the equalization level again. Due to the relatively large bit line capacitance, the current consumption brought about by these charge-reversal operations is substantially determined by the magnitude of the bit line capacitance, whereas the refreshing of the leakage current losses of the storage capacitor is pushed into the background. Thus, the power loss consumption during a refresh cycle is substantially taken up by the parasitic currents for the charge reversal of the bit line capacitances and the provision of these currents from the supply voltage.
When dynamic semiconductor memories are used in devices whose supply voltage is provided by a battery, the battery life is also limited during low-power-loss standby operation. A relatively high power loss is already consumed by the refresh cycles of the dynamic semiconductor memory. It is noticeable that the power loss consumption for the refresh is substantially brought about by the charge reversal of the parasitic bit line capacitance. The possibilities for using dynamic semiconductor memories in power-loss-critical applications are, therefore, limited.
U.S. Pat. No. 5,526,319 to Dennard et al. describes a semiconductor memory having conventional sense amplifiers and, moreover, a cyclic power source. The cyclic power source is connected to an input terminal of the sense amplifier through a switch. The switch is controlled by an enable signal so that the cyclic power source is available for reading out the data on the bit lines.
It is accordingly an object of the invention to provide a semiconductor memory with refresh and method for operating the semiconductor memory that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that has a power loss consumption as low as possible during the refresh.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory including at least one memory cell, a bit line connected to the memory cell, a sense amplifier having an output, the sense amplifier connected to the bit line, amplifying a signal read from the memory cell, and generating, at the output, an output signal derived from the signal, and an adiabatic amplifier connected to the bit line and to the output and driven by the output signal of the sense amplifier to write back the signal read from the memory cell to the memory cell in amplified form dependent upon the output signal of the sense amplifier.
The semiconductor memory has a normal operating mode, in which customary memory accesses, i.e., writing and reading of data values to and from memory cells, are carried out. Also provided is a standby operating mode with relatively low power loss consumption. During the standby operating mode, data are not input or output externally, rather all that is effected is the internal charge retention of the dynamic memory cells. During such a phase, for the purpose of carrying out the refresh operations, the adiabatic amplifier is used so that the bit line capacitances are subjected to charge reversal in a manner exhibiting a low power loss. During the low-power-loss standby operating mode, there is sufficient time available for the adiabatic amplifier to carry out an amplification operation. An amplification operation by the adiabatic amplifier takes longer than an amplification operation carried out by a normal sense amplifier.
In the case of the semiconductor memory according to the invention, an adiabatic amplifier is used for driving an amplified level onto the bit lines. A conventional characteristic of the adiabatic amplifier is that, in the event of a level transition in one direction, at least part of the reduced quantity of charge is buffer-stored in one or more capacitors and is subsequently output again in the event of a level change in the opposite direction. A level change is composed step-by-step of a plurality of charge-reversal operations into a capacitor or from a capacitor onto the circuit node to be subjected to charge reversal. Current is drawn from the supply voltage only for the final charge-reversal step so that the present level is driven fully to the supply voltage. The current consumption for traversing a level swing from the initial level to the target level and back to the initial level consumes only little current on account of the buffer-storage in capacitors. Power loss is thereby saved. Compared with conventional concepts in which the bit line is driven by an inverter, for example, more time is admittedly taken up for the charge transition from the capacitor into the circuit node to be subjected to charge reversal, the bit line in this case. Nevertheless, because there is sufficient cycle time available for a refresh cycle, the longer time duration required by an adiabatic charge-reversal operation compared with conventional concepts is not a hindrance.
Concepts for adiabatic amplifiers are described in the literature reference Luns Tee, Lizhen Zheng xe2x80x9cCharge Recovery and Adiabatic Switching Techniques in Digital Logicxe2x80x9d. Through the use of the adiabatic circuit concept for the charge reversal of the bit lines during a refresh cycle, power loss is substantially saved so that the semiconductor memory can now be used in power-loss-critical systems, for example, in battery-operated devices. A dynamic semiconductor memory can then also be used for the permanent storage of information in battery-operated devices.
The adiabatic amplifier is connected to the bit line on the output side and is driven by the sense amplifier on the input side. The sense amplifier prescribes the level that is to be written back onto the bit line and to the storage capacitor currently being read, and generates the corresponding control signals for the amplification operation. As in the prior art, the bit lines are organized in pairs, a bit line pair being connected to complementary inputs of a sense amplifier and one of the bit lines carrying the information that is to be stored in a non-inverted fashion (true bit line), while the other bit line of the bit line pair carries the information that is to be stored in an inverted fashion (complementary bit line). The adiabatic amplifier is connected to the complementary bit lines on the output side.
In accordance with another feature of the invention, the adiabatic amplifier has first and second output terminals, a further bit line is connected to the sense amplifier, and the first and second output terminals of the adiabatic amplifier are respectively connected to the bit line and the further bit line.
In accordance with a further feature of the invention, the adiabatic amplifier has at least three current paths connected between the bit line and the further bit line, each of the current paths have a series circuit of controlled paths of two transistors with a coupling node, the coupling node of the transistors for two of the current paths is connected to a respective terminal for a supply potential, and a capacitive element is connected to the coupling node of the transistors for another of the current paths.
Preferably, the adiabatic amplifier has at least three current paths connected between the complementary bit lines. Each of the current paths contains the series circuit of the controlled paths, i.e., the drain-source paths, of two transistors. The coupling node of the transistors is connected to the positive supply potential, which forms the high level, in the case of the first of the current paths. The coupling node of the second of the current paths is connected to reference-ground potential or ground, which forms the low level. The coupling node of the transistors of the third current path is connected to a capacitor. At the other ends the capacitor is connected to reference-ground potential or ground. The control terminals of the transistors, i.e., the gate terminals, are controlled by a control device in a suitable manner to carry out a charge-reversal operation. During the charge-reversal operation for a refresh cycle on a memory cell, the bit line, which is initially at an equalization potential preferably lying in the middle between the positive supply potential and ground, is brought to the positive supply potential or to ground potential in a manner dependent on the data value to be restored. Afterward, the bit line is returned from this high or low level to the equalization potential again. The other bit line of the bit line pair undergoes exactly the opposite charge-reversal operation. Because the adiabatic amplifier is connected to the complementary bit lines on the output side and the above-mentioned current paths lie between these terminals, it is advantageously possible for the quantity of charge carried away by one bit line to be buffer-stored in the capacitor in a first operating clock cycle and to be transferred to the other of the bit lines in a subsequent operating clock cycle. The transition to the complete high or low level, that is to say, positive supply potential or ground, is achieved in that the respective bit line is connected to the terminal for the positive supply potential or ground potential, respectively, through the respective switch. Only during this last-mentioned operating clock cycle of the adiabatic amplification is current drawn from the supply voltage. In all other operating clock cycles, the charge is transferred from the bit line into the capacitor or is output from the capacitor onto the other of the bit lines of the bit line pair. As a result, power loss is substantially saved.
In accordance with an additional feature of the invention, the transistors have control terminals and a control device has an output side connected to the control terminals of the transistors to control an adiabatic amplification operation of complementary signals on the bit lines dependent upon the output signal of the sense amplifier.
In accordance with yet another feature of the invention, there are provided further capacitive elements and at least two further current paths are connected between the first and second output terminals, each of the further current paths having two transistors with a coupling node, the two transistors connected in series by controlled paths, the coupling node connected to a respective one of the further capacitive elements.
In continuation of the principle described, even further current paths with series-connected, controlled paths of transistors and capacitors at the coupling node of the transistors can be connected in parallel with the previous current paths, that is to say, between the output terminals of the adiabatic amplifier. By way of example, two further current paths may be provided, or generally an arbitrary number of further current paths connected in parallel. The further current paths form intermediate levels for the level transitions during a charge-reversal operation, once again only the respective final charge-reversal operation to ground potential or to the positive supply potential drawing a current from the supply voltage. By virtue of the further current paths and capacitors, the intermediate level stages are more finely gradated, so that the current loss to be provided from the supply voltage decreases with an increasing number of current paths, because the partial level to be equalized is smaller. By way of example, with a total of five current paths connected in parallel, the current consumption is reduced to just a quarter relative to a conventional concept. Otherwise, the amplification operation is effected by charge-reversal operations between the complementary bit lines. In the case of the above-mentioned five current paths connected in parallel in the adiabatic amplifier, of which two current paths are connected to the poles of the supply voltage and three current paths are connected to a respective capacitor, three intermediate levels lying between a fully driven high level (positive supply voltage) and a fully driven low level (ground) are introduced, namely at 1/4*UH, 1/2*UH, 3/4*UH, where UH is the high level or the positive supply potential.
In accordance with an added feature of the invention, the control device has a read-only memory and a counter connected to and driving the read-only memory and the read-only memory has an output side connected to the control terminals of the transistors.
In accordance with yet a further feature of the invention, the sense amplifier is a plurality of sense amplifiers, a plurality of bit line pairs are respectively connected to one of the sense amplifiers, the adiabatic amplifier is a single adiabatic amplifier with an input side and an output side, the input side of the single adiabatic amplifier is connected to the sense amplifiers, the single adiabatic amplifier is driven by each of the sense amplifiers, at least one controllable switching device is connected to the output side of the single adiabatic amplifier, the switching device is connected to bit lines of the bit line pairs for connecting the output side of the single adiabatic amplifier to the bit lines of the bit line pairs, and the switching device is programmed to drive a respective one of the bit line pairs based upon the output signal from a respective one of the sense amplifiers connected to the one of the bit line pairs and fed to the single adiabatic amplifier by the single adiabatic amplifier through the switching device.
In accordance with yet an added feature of the invention, for an output signal directly sent to the single adiabatic amplifier from one of the sense amplifiers connected to a respective one of the bit line pairs, the switching device is programmed to drive the one of the bit line pairs with the single adiabatic amplifier through the switching device.
In accordance with yet an additional feature of the invention, the memory cell has a selection transistor and a storage capacitor and the adiabatic amplifier refreshes a charge content of the storage capacitor.
For the purpose of driving the switches of the adiabatic amplifier, a counter, for example, is provided, which drives the memory cells of a read-only memory (ROM). The outputs of the read-only memory are connected to the gate terminals of the transistors of the adiabatic amplifier and are switched on and off in a manner dependent on the data values read from the read-only memory. The counter is triggered by a refresh signal. The sequence of control signals for driving the transistors that is to be read from the read-only memory depends on the charge-reversal operation to be carried out, that is to say, on the state of the data value to be refreshed. This information is supplied by the sense amplifier, which is also connected to the bit line pair, and is communicated to the read-only memory at one of its address inputs.
Compared with a conventional inverter stage for driving a bit line for the charge reversal during a refresh cycle, an adiabatic amplifier has a larger number of components and, consequently, a larger area occupation in an integrated realization on the semiconductor memory chip. However, it suffices for the adiabatic amplifier to be associated with a multiplicity of bit line pairs for carrying out the refresh operation. Thus, only a single adiabatic amplifier is provided for the multiplicity of bit line pairs, which amplifier, on the input side, is driven by the sense amplifiers respectively connected to the bit line pairs and which amplifier, on the output side, is in each case only ever connected, through corresponding switching device, to one of the bit line pairs, namely that pair by whose connected sense amplifier it is currently being driven on the input side. The data value to be refreshed is then communicated to the single adiabatic amplifier through the respective sense amplifier, with the result that the switching device, e.g., a demultiplexer, connects the output of the adiabatic amplifier to the bit line pair to which the memory cell to be refreshed is connected. Therefore, the adiabatic amplifier can be used jointly for a multiplicity of bit line pairs. Because the memory cells are organized in blocks, adiabatic amplifiers can be used jointly for the refresh operation of different blocks. It is also expedient within a block to associate an adiabatic amplifier to a plurality of bit line pairs.
With the objects of the invention in view, there is also provided a two-mode semiconductor memory including at least one memory cell having a selection transistor and a storage capacitor, a bit line connected to the memory cell, a sense amplifier having an output, the sense amplifier connected to the bit line, amplifying a signal read from the memory cell, and generating, at the output, an output signal derived from the signal, an adiabatic amplifier connected to the bit line and to the output and driven by the output signal of the sense amplifier to write back the signal read from the memory cell to the memory cell in amplified form dependent upon the output signal of the sense amplifier, the adiabatic amplifier refreshing a charge content of the storage capacitor, and a first operating mode carrying out a reading or writing access of a data value at the memory cell with a relatively high power loss consumption and a second operating mode refreshing the data value stored in the memory cell through the adiabatic amplifier with a relatively lower power loss consumption.
In accordance with again another feature of the invention, the second operating mode refreshes the data value with relatively substantially lower power loss consumption
With the objects of the invention in view, there is also provided a method for operating a semiconductor memory including the steps of providing a two-mode semiconductor memory having at least one memory cell, a bit line connected to the memory cell, a sense amplifier having an output, the sense amplifier connected to the bit line, and an adiabatic amplifier connected to the bit line and to the output of the sense amplifier, generating an output signal derived from the signal at the output of the sense amplifier, in a first operating mode, amplifying a signal read from the memory cell with the sense amplifier and providing the signal at an external output terminal of the semiconductor memory, and in a second operating mode, feeding the output signal of the sense amplifier to the adiabatic sense amplifier to control, dependent upon the output signal of the sense amplifier, the adiabatic sense amplifier such that the signal read from the memory cell is written back to the memory cell again after adiabatic amplification.
In accordance with again a further mode of the invention, the first operating mode is carried out as a normal operating mode of the memory and the second operating mode is carried out as a power-saving mode of the memory, the power-saving mode having a relatively lower power loss compared to a power loss of the normal operating mode.
In accordance with a concomitant mode of the invention, the first operating mode is a normal operating mode of the memory and the second operating mode is a power-saving mode of the memory having a relatively lower power loss compared to a power loss of the normal operating mode.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory with refresh and method for operating the semiconductor memory, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.